1. Technical Field
This invention relates generally to charge pump systems and more particularly, relates to fast settling phase lock loop systems with a charge pump.
2. Related Art
Phase locked loop (PLL) circuits are widely used in many different applications. Five applications of PLL circuits are (1) to lock or align the output clock of a circuit with the clock input, (2) to multiply (i.e., increase) or divide (i.e., decrease) the output frequency of a circuit with respect to the input frequency, (3) to provide clock recovery from signal noise, (4) frequency synthesis, and (5) clock distribution. A PLL circuit controls the frequency of a voltage-controlled oscillator (VCO) such that the VCO provides an output frequency that is adjusted to stay in sync with a reference signal.
A PLL commonly includes a phase detector or phase-frequency detector (PFD), that compares two input signals, a reference signal and a signal from the VCO. The PFD then provides an output of positive or negative pulses, depending on which of the inputs leads the other in phase. The output of the phase detector (PFD), which is an error signal, must then be integrated to provide a control voltage for the VCO. As the error signal approaches zero, the integrator output becomes constant and the VCO frequency is held at a fixed value. When the VCO frequency is held at a fixed value, the PLL is in the xe2x80x9clockedxe2x80x9d condition. A method of implementing the integration step is to utilize a loop filter, which is commonly an active low-pass filter. The loop filter integrates the voltage pulses from the phase detector (PFD) and provides a steady DC voltage output to the VCO.
A lower cost method of integrating the voltage pulses is to have a charge pump connected with the output of the phase detector. The charge pump generates current pulses that can be integrated by charging a capacitor. In this method, the loop filter is a passive low-pass RC filter. Such a loop filter integrates the current pulses and provides a steady DC voltage that controls the VCO.
A charge pump charges and discharges a loop filter based on the phase difference between the input signals to the charge pump. A conventional pump provides an output current that is the difference between an up-current from a current source connected with a supply voltage and a down-current from a current source (current sink) connected with ground. A transistor turns the current source xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d and charges the output node, by charging the loop filter which increases the output voltage. Another transistor turns xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d the currents ink and discharges the output node, by discharging the loop filter which decreases the output voltage. During times that neither charging nor discharging is required, the charge pump presents a high impedance to the loop filter to prevent the loop filter from discharging. Such a high impedance is commonly implemented by (1) turning off the current source and current sink, or (2) turning on the current source and the current sink. When the current source and current sink are turned off, the impedance of the current source and the current sink in the off state must be extremely high. When the current source and the current sink are turned on, the up and down currents must be substantially matched. The matched currents prevent unwanted charging or discharging of the loop filter and maintains a constant output voltage from the loop filter.
When a conventional PLL with a charge pump is locked, any mismatch in the current source results in a leakage to or from the loop filter that results in sideband tones, also called spurs, in the output signal. A perfectly matched charge pump in the locked condition would not output charge pulses, because the VCO control voltage would remain constant without the need to refresh the loop filter. If the charge pump is not perfectly matched some leakage will occur. The leakage requires the loop filter to be refreshed. A larger leakage require a larger refresh current. To generate a larger refresh current, the charge pump must source or sink current with a larger duty cycle. When a conventional charge pump""s control signals are switched on and off at a rate called the xe2x80x9ccomparison frequencyxe2x80x9d, a refresh charge injection results in undesirable fluctuations in the voltage from the loop filter to the VCO. The refresh charge injection causes undesirable fluctuations in the output frequency from the VCO. Such fluctuations occur at comparison frequency and generate sideband spurs. The sideband spurs occur at frequencies spaced from the VCO""s main output frequency by an amount equal to the comparison frequency. The sideband spurs tend to occur equally above and below the VCO""s main output frequency.
The VCO output frequency varies based on an input voltage. A VCO typically outputs a sine wave. As the input voltage to the VCO increases, the output frequency from the VCO also increases. The dynamic range oft he output voltage of a charge pump is an important factor in determining the maximum range and accuracy of the lock frequencies of the PLL.
Conventional PLLs generate undesired spectra (noise), such as spurious sideband tones, phase noise, and switching noise. The undesired spectra in the PLL""s output signal generally includes glitches of energy, especially spurious sideband signals, discrete tones, and spread-frequency noise. In a PLL, the unwanted tones and noise may be created by a clock source feed through, charge injection at a P-type Mosfet (PMOS) or N-type Mosfet (NMOS) switching transistor, or another source. Also, the switching nodes of conventional charge pumps often have charge sharing resulting from parasitic capacitance.
The settling time of a PLL can be reduced by adjusting the PLL""s bandwidth during the settling process. The settling time is the time required for the PLL to change frequencies. To improve the settling time, the resistance of the loop filter may be adjusted by switching an additional resistor into the loop filter""s RC circuit during the settling process. The additional resistor is switched into the RC circuit at a predetermined time during the settling process. Alternatively, the additional resistor is switched into the RC circuit during the settling process when the charge pump causes a step change in the charge pump current. These processes attempt to narrow the PLL""s bandwidth after much of the settling process is completed. Such switching in the loop filter and the charge pump cause undesirable large transient signals in the loop filter""s output. The transients cause the PLL""s frequency of the output signal to fluctuate jump away) from the desired frequency, causing the settling time of the PLL to increase, thereby defeating the purpose of the switching.
Alternatively, the settling time of a PLL can be reduced by increasing the reference clock""s frequency and/or using a fractional-N PLL. These options allow a wider loop bandwidth and increases the speed of the PLL. The phase and frequency detector (PFD) in these options requires additional circuitry to handle the increased frequency. A PLL with a wider loop bandwidth that is a fixed width is not be desirable, because the in-band noise from the phase detector and the main frequency divider are positively correlated to the loop bandwidth. That is, a wider loop bandwidth results in increased in-band noise.
It is therefore desirable to have a PLL with a charge pump that settles to new frequencies quickly without generating transients, and without requiring an excessive width fixed loop bandwidth when the PLL is in the settled (xe2x80x9clockedxe2x80x9d) state. Further limitations and disadvantages of conventional systems will become apparent to one of skill in the-art after reviewing the remainder of this patent application with reference to the drawings.
This invention provides a charge pump biasing circuit that varies the bias when the phase lock loop changes frequency to improve the settling time of the phase lock loop. During a frequency change, the charge pump output current taper off as the phase lock loop approaches the desired frequency. The charge pump biasing circuit allows the phase lock loop to change frequencies faster and minimizes spurious sideband noise once the loop has settled.
Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.